1. Field of the Invention
The present invention relates to a switched capacitor type digital-analog converter, in which a selective activation of a capacitor enables a digital signal to be converted into an analog signal.
2. Description of the Related Art
A liquid crystal display (LCD) panel is used in a display of a note type computer. The LCD panel is also used as a monitor for a desktop type computer. A monitor comprising the LCD panel (LCD type monitor) is used as a variation of a CRT type monitor. A specification similar to that of the CRT is established for the LCD panel comprised by the LCD type monitor. The specification implies, for example, a screen size, a detailed degree, an image quality, a view angle and a gradient. It is necessary to satisfy the specification at a low cost in order that the LCD type monitor is popularized as the variation of the CRT type monitor.
A thin film transistor (TFT) type drive circuit (module) to drive a liquid crystal is used in the LCD panel.
FIG. 1 shows the configuration of a known TFT type LCD module. An LCD module 120 in FIG. 1 is provided with a y correction circuit 121, a signal converter 122, a source driver 123, a gate driver 124 and an LCD panel 125. An image signal (IMS) from a computer is applied to the signal converter 122.
FIG. 2 shows the configuration of a known LCD panel. An LCD panel 125 in FIG. 2 is provided with a plurality of transistor circuits 130. The transistor circuit 130 is composed of a transistor 131 and a capacitor 132.
FIG. 3 shows the configuration of a known source driver. A source driver 123 in FIG. 3 is composed of a shift register SReg, a data register DReg, a data latch DLat and a digital-analog converter DAC. To the source driver 123, a start signal SS, an outputting timing signal TS, a digital input signal SID and a reference voltage RV is applied. From the source driver 123, a cascade output signal OUT is outputted.
A fast operation and a high drive performance are set for the illustrated source driver 123 (TFT drive circuit) in order to satisfy the screen size and the detailed degree. A dynamic range between 10 and 15 V is set for the TFT drive circuit, in order to satisfy the image quality and the view angle. A digital-analog conversion performance of at least 8 bits is set for the TFT drive circuit in order to satisfy the specification with regard to the gradient.
FIG. 4 shows an operation of a dot inversion drive mode of the known TFT drive circuit. FIG. 4 shows an operation in which a plus and a minus are inverted for each dot.
A common voltage Vcom is kept constant in the dot inversion drive mode. A voltage VLCD which is applied to a liquid crystal is changed between a positive side voltage V+ and a negative side voltage V- with the common voltage Vcom as a boundary. The positive side voltage V+ is a drive voltage higher than the common voltage Vcom. The negative side voltage V- is a drive voltage lower than the common voltage Vcom.
In the dot inversion drive mode, an 8-bit digital-analog converter is used for each of the positive side voltage V+ (f1, f3, . . . )and the negative side voltage V- (f2, . . . ) for the frame F1 and F2.
FIG. 5 shows an operation of a line inversion drive mode of the known TFT drive circuit. FIG. 5 shows an operation in which a plus and a minus are inverted for each line.
In the line inversion drive mode, a common voltage Vcom is varied for each line. When this common voltage Vcom is varied, a voltage VLCD which is applied to the liquid crystal is set at a positive side voltage V+ and a negative side voltage V-. The variation range between the positive side voltage V+ and the negative side voltage V- is equal to the common voltage Vcom. The positive side voltage V+ is a drive voltage when the common voltage Vcom is low. The negative side voltage V- is a drive voltage when the common voltage Vcom is high.
In the line inversion drive mode, one 8-bit digital-analog converter is used in the whole of the positive side voltage V+ (f1, f3, . . . )and the negative side voltage V- (f2, . . . ) for frame F1, F2.
A TFT drive circuit operated at the dot inversion drive mode employs a digital-analog converter equal to two times the TFT drive circuit operated at the line inversion drive mode.
FIG. 6 shows a known digital-analog converter. The digital-analog converter in FIG. 6 is a switched capacitor type.
A switched capacitor type digital-analog converter 170 is provided with a high voltage process HP. Further more, the converter 170 is provided with an input capacitor 171-0, shared input capacitors 171-1 to 171-n, an output capacitor 172, switches 173-1 to 173-n, switches 174-1 to 174-n, an input switch 175, a reference voltage switch 176, a short-circuit switch 177, an output switch 178 and an operational amplifier 179.
A first voltage V1 is applied to the switches 173-1 to 173-n. Outputs of the switches 173-1 to 173-n are connected to inputs of the shared input capacitors 171-1 to 171-n. Outputs of the shared input capacitors 171-1 to 171-n are connected to an inversion input of the operational amplifier 179. The outputs of the shared input capacitors 171-1 to 171-n are connected to an input of the short-circuit switch 177. An output of the output capacitor 172 is connected to an output of the operational amplifier 179. An output of the short-circuit switch 177 is connected to the output of the operational amplifier 179. And, the output of the operational amplifier 179 is connected to an input of the output switch 178.
A second voltage V2 is applied to the input switch 175. An output of the input switch 175 is connected to an output of the reference voltage switch 176. An output of the input switch 175 is connected to an input of the input capacitor 171-0. The output of the input switch 175 is connected to inputs of the switches 174-1 to 174-n. Outputs of the switches 174-1 to 174-n are connected to the inputs of the shared input capacitors 171-1 to 171-n. An output of the input capacitor 171-0 is connected to the inversion input of the operational amplifier 179. A reference voltage Vr is applied to an input of the reference voltage switch 176. The input of the reference voltage switch 176 is connected to a non-inversion input of the operational amplifier 179. The switch has the configuration in which a p-channel transistor and an N-channel transistor are combined. The switch is set ON if the input is at a high level.
The switched capacitor type digital-analog converter 170 corresponds to an output of a positive side voltage for Vcom and an output of a negative side voltage for Vcom. The first voltage V1 is higher than the second voltage V2. Capacitances C0, C1 of the capacitors 171-0, 171-1 are a standard capacitance C. A capacitance C2 of the capacitor 171-2 is C2=2.times.C. A capacitance C3 of the capacitor 171-3 is C3=2.times.2.times.C. A capacitance of the capacitor 171-n is Cn=2.sup.n-1.times.C(n.ltoreq.1). A capacitance Cc of the output capacitor 172 is Cc=2.sup.n.times.C.
If the switched capacitor type digital-analog converter 170 is at an output state, the short-circuit switch 177 and the reference voltage switch 176 are set OFF, and the output switch 178 and the input switch 175 are set ON. If the switches 173-1 to 173-n are set ON, the switches 174-1 to 174-n are set OFF. If the switches 173-1 to 173-n are set OFF, the switches 174-1 to 174-n are set ON.
An output voltage Vo can be represented by the equation (1): EQU Vo=2.times.Vr-(V2+(.alpha./2.sup.n).times.(V1-V2)) (1)
Here, .alpha. is a value of an inputted input data, and indicates a numeral between 0 and (2.sup.n -1) . In a case of 8 bits, it indicates .alpha.=0 to 255.
If the switched capacitor type digital-analog converter 170 is at a reset state, the short-circuit switch 177 and the reference voltage switch 176 are set ON, and the output switch 178 and the input switch 177 are set OFF. The switches 173-1 to 173-n are set OFF, and the switches 174-1 to 174-n are set ON. The switched capacitor type digital-analog converter 170 constitutes a voltage follower. The reference voltage Vr is applied to the inversion input of the operational amplifier 179. Potentials of the input capacitors 171-0 to 171-n and a potential of the output capacitor 172 indicate the reference voltage Vr. Charges are not accumulated in the input capacitors 171-0 to 171-n and the output capacitor 172.
If the switched capacitor type digital-analog converter 170 is at the output state, the short-circuit switch 177 and the reference voltage switch 176 are set OFF, and the output switch 178 and the input switch 177 are set OFF. The switches 173-1 to 173-n and the switches 174-1 to 174-n are set ON or OFF.
The total capacitance of the input capacitors which are activated by the switches 173-1 to 173-n and to which the first voltage V1 is applied is represented by (.alpha..times.C). The total capacitance of the input capacitors which are activated by the switches 174-1 to 174-n and to which the second voltage V2 is applied is represented by ((2.sup.n -.alpha.).times.C). Va denotes a potential of the inversion input of the operational amplifier 179. Charges accumulated in the input capacitors 171-0 to 171-n and the output capacitor 172 can be represented by the equation (2): EQU (Va-V).times..alpha..times.C+(Va-V2).times.(2n-.alpha.).times.C+(Va-V0).tim es.C (2)
The voltage Vr is applied to the non-inversion input of the operational amplifier 179. The voltage Va indicates a value equal to the voltage Vr. Charges of the inversion input at the operational amplifier 179 are held in the reset state and the output state. The accumulated charge at the reset state is zero, and the charge at the output state is represented by the equation (2). Thus, from a charge conservation principle, the equation (3) can be obtained: EQU 0=(Va-V1).times..alpha..times.C+(Va-V2).times.(2.sup.n -.alpha.).times.C+(Va-Vo).times.Cc (3)
The equation (1) is obtained by substituting Cc=2.sup.n.times.C into the equation (3).
The techniques with regard to the switched capacitor type digital-analog converter are disclosed in Japanese Laid Open Patent Application (JP-A-H2-266330), Japanese Laid Open Patent Application (JP-A-H5-136696), Japanese Laid Open Patent Application (JP-A-H5-259917) Japanese Laid Open Patent Application (JP-A-H5-268097) and Japanese Laid Open Patent Application (JP-A-H8-106077).
The switched capacitor type digital-analog converter 170 equally divides a potential difference between the first voltage V1 and the second voltage V2. The first and second voltages V1, V2 are used to reproduce a voltage-transmission curve of the liquid crystal panel. When the dynamic range of the output voltage Vo is set between 10 and 15 V, the first and second voltages V1, V2 and the reference voltage Vr are set to be higher than 5 V.
The switches 173-1 to 173-n, the switches 174-1 to 174-n, the input switch 175 and the reference voltage switch 176 which correspond to a voltage equal to or higher than 5 V are high voltage transistors. The high voltage transistor has a wide exclusive area. The high voltage transistor disturbs the miniaturization of the switched capacitor type digital-analog converter. Especially, the high voltage transistor is an obstacle to a reduction in a chip size of an LCD driver which uses a large number of switched capacitor type digital-analog converters. Also, the high voltage transistor is an obstacle to a drop in a consumptive electric power of the digital-analog converter. Moreover, when the high voltage transistor is used, a drive signal of a high voltage must be used to drive the switch of the digital-analog converter. The drive signal of the high voltage requires a high electric power. As a result, the high voltage transistor is an obstacle to a drop in a consumptive electric power of a drive circuit for generating a drive signal.